Design Verification Engineer
Design Verification Engineer
Dwebtech Consulting Inc.
San Francisco Bay Area
See who Dwebtech Consulting Inc. has hired for this role
Position: Design Verification Engineer
Location: Bay Area, CA (Hybrid)
Duration: Long-term
Required skill is - PCIe or NVMe exp and Hybrid in
Job Description
Location: Bay Area, CA (Hybrid)
Duration: Long-term
Required skill is - PCIe or NVMe exp and Hybrid in
Job Description
- Conduct thorough verification of RTL implementation for intricate digital blocks to ensure optimal functionality and quality standards.
- Formulate comprehensive verification strategies for novel features, including devising plans for volume validation and coverage assessment.
- Create detailed test plans, develop robust testbenches, and implement test sequences and checkers utilizing System Verilog & UVM for IP-level verification within constrained-random and directed verification environments.
- Collaborate closely with design teams to analyze coverage metrics and implement corrective actions to achieve coverage objectives.
- Integrate Verification IP (VIPs) as necessary to enhance verification processes and efficiency.
- Actively engage with design teams to facilitate feature implementation and seamless integration of verified components.
- Demonstrated working experience with NVMe and/or PCIe, DMA protocols.
- Proficiency in bus protocols such as AXI/AHB is highly desirable.
- Hands-on experience in developing UVM/OVM and/or Verilog/System Verilog test benches and BFMs from scratch.
- Strong understanding of simulation tools and proficient in scripting languages like Perl, Tcl, or cshell.
- Proven ability to work autonomously and effectively in a dynamic, fast-paced team environment, demonstrating high motivation and self-initiative.
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Seniority level
Mid-Senior level -
Employment type
Contract -
Job function
Engineering and Information Technology -
Industries
Industrial Machinery Manufacturing
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